The present invention can be applied to any appropriate memory structure wherein each column comprises a plurality of memory cells connected to a single bit line, and is not restricted to any specific structure of memory cell. However, the invention has particular advantage in an electrically erasable flash memory having single transistor cells with a floating gate. It is desirable to use a dynamic sense amplifier for sensing data from memory cells in a flash memory. However, as is known, a sense amplifier in a flash memory compares a reference current with a current on the bit line connected to an addressed memory cell.
The reference current I REF supplied to the sense amplifier can be taken from any convenient source on chip. However, there is a problem if the capacitance associated with the source for the reference current I REF differs significantly from the capacitance of the bit line to which the selected cell is connected. Capacitive balancing is needed for good sensing. However, this is not simple to achieve in a single transistor flash EPROM. As each cell contains only one transistor, it is not possible to use a folded bit line scheme as is implemented commonly on dynamic random access memories (DRAMs). Furthermore, although in principle a dummy bit line could be used in association with each active bit line per column, this would increase the required space in the layout and make the chip much larger. The difficulty of achieving proper capacitive balancing in a single transistor flash EPROM has meant that the sense amplifier has conventionally been a static sense amplifier, for which the output will eventually settle at the correct state even after initial noise. For the reasons given above, it has not been possible to use a dynamic sense amplifier on a single transistor flash EPROM, because these amplifiers are particularly sensitive to initial noise, which could cause the dynamic sense amplifier to latch in an incorrect state.